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Last Updated: Feb 18th, 2008 - 14:39:01 |
VoIP Gateway Hardware Architecture
The issue of gateway scalability is rooted in system design and architecture, both hardware and software. Specifically, the design tradeoffs you make while architecting a gateway may limit or enhance your ability to scale upwards. Further, design decisions can lead to implementations appropriate for a given target density or port count. If your goal is to create a scaleable, high-density gateway, you must be aware of several important design tradeoffs and consequences.
Host-Based Versus DSP-Based Compression
The first generation of gateway products uses the host CPU to do everything, from running the application to performing all call control, compression, and packetization. Due to the tremendous processing burden placed on the host CPU, especially the compute-intensive task of voice compression for which it is ill-suited, such a gateway is quickly limited by its CPU speed. To combat this limitation, many pioneering gateway technology providers use proprietary, relatively non-complex voice compression algorithms. Nonetheless, industry leader VocalTec can only support up to 8 ports in a gateway powered by a Pentium 200 MHz using host-based compression.
Given that Intel recommends a 100 MHz Pentium CPU to support a single user of its G.723 standards-based Internet Phone, it stands to reason that, at most, a handful of G.723 ports could be supported by host-based compression.
Second-generation gateway technology suppliers favor DSP-based compression. As illustrated in Figure 3, a DSP resource board is added to the gateway server to off-load the processing intensive tasks best handled by a DSP processor. These tasks include voice compression, echo cancellation, and DTMF carriage.
The DSP resource board is most likely connected to the telephony interface board using a time division multiplexed (TDM) bus, typically MVIP or SCSA. The TDM bus delivers uncompressed 64-kbps PCM data to the DSP board where it is compressed and packetized. A hidden benefit of off-loading the CPU from the compression task comes in the decrease in data transfer rate, typically 10:1 or more, by passing compressed voice across the ISA bus. When the host CPU is transferring uncompressed voice to and from the telephony board at 64 kbps per port, an order of magnitude more CPU and bus bandwidth is utilized than when compressed voice is transferred to and from the DSP board at 4-8 kbps per port.
A DSP resource board is typically composed of many DSP processors, each capable of handling multiple ports of voice compression and related processing. This leads to a gateway architecture which provides higher per-gateway port densities which can be easily scaled by adding more DSP resource boards. As many high-density boards are combined in a system, however, the issue of CPU and bus bandwidth again comes into play due to the sheer port count. The system integrator must pay special attention to the efficiency of the DSP board's host drivers in order to determine the practical limit of the system.
Host-Based Versus Embedded Protocol Stacks
Perhaps not as obvious as the issue of host-based compression is the issue of host-based protocol stacks. If you were to relieve the CPU of the DSP-related tasks, you would find that the computational load of running many channels of the relevant H.323, stack components was significant. Most gateway technology suppliers utilize inexpensive Ethernet NICs with just enough computational capacity to run the TCP/IP stack the H.245, H.225, and RTP/RTCP protocols are run on the host CPU. This arrangement suffices for a few ports, maybe even as many as 24 or 30. Any more ports, however, and this arrangement soon proves inadequate as most of the CPU's bandwidth is consumed.
Several possible solutions to this limitation are proposed. One concerns protocol stacks. The H.323 stacks and most TCP/IP stacks have not been designed to handle hundreds or thousands of low-bandwidth communications channels. They have, in fact, been designed and engineered to handle a few high-bandwidth packet data streams. This heritage does not lend itself to meeting the requirements of a high-density, scaleable VoIP gateway. The use of protocol stacks specifically optimized to the needs of multi-port, real-time communications channels would go a long way toward minimizing the impact of running a host-based protocol engine.
To achieve the highest density, a scaleable gateway would require the use of a separate embedded processor for the protocol stacks, just as the DSP resource board is used for voice compression. With the processing burden of many ports of the H.323 and underlying protocol stacks removed from the host CPU, it would simply monitor and control the IP subsystem with minimal effort. As the gateway scaled up to high port counts, additional embedded processors would be added to handle the increased protocol demand.
ISA Versus PCI Versus TDM
The issue of data transfer throughout the gateway is another determinant in overall system performance and scalability. The real driver behind which bus to use for system data transfer is not bus bandwidth, but once again CPU loading. The burden on the host CPU from data transfer is much more significant than the actual bus bandwidth limitation in the gateway.
For example, an 8-kbps (1-kB/sec) voice codec with 50 percent silence suppression and RTP/RTCP packet overhead produces approximately a 1-kB/sec data stream. Therefore, passing 100 ports of compressed voice packets to and from the host CPU requires only about 200 kB/sec (=1 kB/sec x 100 x 2 transfers), well below the capabilities of even the ISA bus. For systems handling thousands of ports, a PCI bus architecture would still have plenty of headroom. As we can see, the raw bus bandwidth required by high-density, scaleable gateways can be met by the ISA and PCI buses.
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